1. Field of Invention
The present invention relates to a method of fabricating shallow trench isolations (STI). More particularly, the present invention relates to a method of fabricating the STI, which method solves the problems of microscratch and dislocation.
2. Description of Related Art
Implementing electric circuits involves connecting isolated devices through specific electrical paths, it is therefore be possible to isolate devices built into the silicon from one another when fabricating silicon integrated circuits. With advent of integrated circuits, it became necessary to provide electrical isolation between the devices fabricated on the same piece of silicon. One of the most important techniques developed conventionally for latchup protection was termed local oxidation of silicon (LOCOS) isolation, which involved the formation of a semirecessed oxide in the nonactive areas of the substrate.
As device geometries reached submicron size, conventional LOCOS isolation technologies reached the limits of their effectiveness, and alternative isolation processes were needed. Newer approach, such as shallow trench isolation, where shallow, refilled trenches are used primarily for isolating devices of the same type, is adopted to overcome some drawbacks of conventional LOCOS for small-geometry devices.
FIGS. 1A and 1B are cross-sectional views of two conventional STI structures refilled with different oxide layers. Referring to FIG. 1A, a buried-oxide (BOX) isolation technology is adopted to form a conventional STI. A substrate 100a is provided with a pad oxide layer 102a and a silicon nitride layer 104a formed thereon, wherein the pad oxide layer 102a serves to cushion the transition of stresses between the substrate 100a and the silicon nitride layer 104a. Active regions (not shown) on the substrate 100a are defined with a photolithographic step, followed by etching a part of the pad oxide layer 102a and silicon nitride layer 104a to form openings (not shown). The openings are then over-etched to form trenches 106a in the substrate 100a, and the trenches 106a are refilled by forming a layer of silicon oxide 108a globally on the silicon nitride layer 104a. The method for forming the silicon oxide layer 108a includes chemical vapor deposition (CVD). The silicon oxide layer 108a is then planarized by chemical mechanical polishing (CMP), so that a part of the silicon oxide layer 108a is removed until the silicon nitride layer 104a is exposed. However, particles in the CMP slurry can damage the surface of the silicon oxide layer 108a, causing defects known as microscratches after CMP is performed. Furthermore, a portion of the silicon oxide layer 108a is lost during a cleaning step, thus creating problem to control the profile of the STI.
A method to densify the silicon oxide layer was then suggested to solve the problem mentioned above and it is best illustrated in FIG. 1B. Accordingly, the conventional method for forming the silicon oxide layer is modified to solve the problem of microscratches resulted from CMP. From the diagram, an additional thermal treatment, such as thermal annealing, is performed to the silicon oxide layer so as to harden the silicon oxide layer 108b. Inevitably, there are also problems associated with this annealing technique as a harder silicon oxide layer creates stresses at the bottom of the STI. The stresses cause dislocations by compressing or distending a crystalline lattice of the substrate 100b, while the dislocations can interact with each other to affect the mechanical and electrical characteristics of the STI.